使用VHDL语言编写的简易数字存储示波器，用MAX+PlusII仿真验证。VHDL编写了采样、存储写、存储读和显示4个模块。采样使用ADC0809，存储器使用6264，显示使用DAC0832。-The design of the chip as a high-speed signal ADC0809 the A/D converter, SRAM6264 memory for data storage after sampling, DAC0832 chip as a signal of D/A

ADC0809 VHDL代码的顺序控制、输入时钟模块默认为100赫兹 -ADC0809 VHDL code of sequence control, the input clock module defaults to 100 hz